72 MHz clock (HSE+PLL), timer experiments

This commit is contained in:
Jörn-Michael Miehe 2024-02-28 13:02:02 +00:00
parent d657238c0c
commit 0225e6d074

View file

@ -14,7 +14,7 @@ use panic_halt as _;
use nb::block;
use cortex_m_rt::entry;
use stm32f1xx_hal::{pac, prelude::*, timer::Timer};
use stm32f1xx_hal::{pac, prelude::*, rcc::Config, timer::Timer};
#[entry]
fn main() -> ! {
@ -30,7 +30,20 @@ fn main() -> ! {
// Freeze the configuration of all the clocks in the system and store the frozen frequencies in
// `clocks`
let clocks = rcc.cfgr.freeze(&mut flash.acr);
let clocks = rcc.cfgr.freeze_with_config(
Config {
// HSE frequency
hse: Some(8_000_000),
// PLLMUL represented by an integer -2
pllmul: Some(9 - 2),
// PCLK1 freq must be 36 MHz or less
ppre1: stm32f1xx_hal::rcc::PPre::Div2,
// ADCCLK freq must be 14 MHz or less
adcpre: pac::rcc::cfgr::ADCPRE_A::Div6,
..Default::default()
},
&mut flash.acr,
);
// Acquire the GPIOC peripheral
let mut gpioc = dp.GPIOC.split();
@ -38,15 +51,27 @@ fn main() -> ! {
// Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the function
// in order to configure the port. For pins 0-7, crl should be passed instead.
let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
// Configure the syst timer to trigger an update every second
let mut timer = Timer::syst(cp.SYST, &clocks).counter_hz();
timer.start(1.Hz()).unwrap();
// at 72 MHz, timer of 1 Hz overflows, use 10 Hz instead (8 Hz experimental minimum)
timer.start(10.Hz()).unwrap();
// equivalent timers:
// let mut timer = Timer::syst(cp.SYST, &clocks).counter_us(); // us resolution
// let mut timer: SysCounter<1000> = Timer::syst(cp.SYST, &clocks).counter(); // ms resolution
// timer.start(100.millis()).unwrap();
// Wait for the timer to trigger an update and change the state of the LED
loop {
for _ in 0..10 {
block!(timer.wait()).unwrap();
}
led.set_high();
for _ in 0..10 {
block!(timer.wait()).unwrap();
}
led.set_low();
}
}