72 MHz clock (HSE+PLL), timer experiments
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d657238c0c
commit
0225e6d074
1 changed files with 30 additions and 5 deletions
31
src/main.rs
31
src/main.rs
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@ -14,7 +14,7 @@ use panic_halt as _;
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use nb::block;
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use cortex_m_rt::entry;
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use stm32f1xx_hal::{pac, prelude::*, timer::Timer};
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use stm32f1xx_hal::{pac, prelude::*, rcc::Config, timer::Timer};
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#[entry]
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fn main() -> ! {
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@ -30,7 +30,20 @@ fn main() -> ! {
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// Freeze the configuration of all the clocks in the system and store the frozen frequencies in
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// `clocks`
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let clocks = rcc.cfgr.freeze(&mut flash.acr);
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let clocks = rcc.cfgr.freeze_with_config(
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Config {
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// HSE frequency
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hse: Some(8_000_000),
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// PLLMUL represented by an integer -2
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pllmul: Some(9 - 2),
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// PCLK1 freq must be 36 MHz or less
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ppre1: stm32f1xx_hal::rcc::PPre::Div2,
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// ADCCLK freq must be 14 MHz or less
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adcpre: pac::rcc::cfgr::ADCPRE_A::Div6,
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..Default::default()
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},
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&mut flash.acr,
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);
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// Acquire the GPIOC peripheral
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let mut gpioc = dp.GPIOC.split();
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@ -38,15 +51,27 @@ fn main() -> ! {
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// Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the function
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// in order to configure the port. For pins 0-7, crl should be passed instead.
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let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
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// Configure the syst timer to trigger an update every second
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let mut timer = Timer::syst(cp.SYST, &clocks).counter_hz();
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timer.start(1.Hz()).unwrap();
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// at 72 MHz, timer of 1 Hz overflows, use 10 Hz instead (8 Hz experimental minimum)
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timer.start(10.Hz()).unwrap();
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// equivalent timers:
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// let mut timer = Timer::syst(cp.SYST, &clocks).counter_us(); // us resolution
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// let mut timer: SysCounter<1000> = Timer::syst(cp.SYST, &clocks).counter(); // ms resolution
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// timer.start(100.millis()).unwrap();
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// Wait for the timer to trigger an update and change the state of the LED
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loop {
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for _ in 0..10 {
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block!(timer.wait()).unwrap();
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}
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led.set_high();
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for _ in 0..10 {
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block!(timer.wait()).unwrap();
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}
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led.set_low();
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}
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}
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