move dmx2 -> dmx
This commit is contained in:
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08db62f4f9
commit
28f3f9f355
3 changed files with 123 additions and 181 deletions
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@ -1,57 +1,142 @@
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use cortex_m::singleton;
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use stm32f1xx_hal::{dma, pac, prelude::*, rcc, serial};
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use stm32f1xx_hal::{afio, dma, gpio, pac, prelude::*, rcc, serial};
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const DMX_LEN_MAX: usize = 512;
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type TxDma = dma::TxDma<serial::Tx<pac::USART1>, dma::dma1::C4>;
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type DMXUniverse<const DMX_LEN: usize> = &'static mut [u8; DMX_LEN];
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type DMXTransfer<const DMX_LEN: usize> = dma::Transfer<dma::R, DMXUniverse<DMX_LEN>, TxDma>;
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pub enum DMX<const DMX_LEN: usize = DMX_LEN_MAX> {
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Idle(Option<TxDma>, Option<DMXUniverse<DMX_LEN>>),
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Busy(Option<DMXTransfer<DMX_LEN>>),
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struct TxDMAIdle<const DMX_LEN: usize> {
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tx: TxDma,
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buffer: DMXUniverse<DMX_LEN>,
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}
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struct TxDMABusy<const DMX_LEN: usize> {
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transfer: DMXTransfer<DMX_LEN>,
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}
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enum TxDMA<const DMX_LEN: usize> {
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Idle(Option<TxDMAIdle<DMX_LEN>>),
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Busy(Option<TxDMABusy<DMX_LEN>>),
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}
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impl<const DMX_LEN: usize> TxDMA<DMX_LEN> {
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fn new(tx: TxDma, buffer: DMXUniverse<DMX_LEN>) -> Self {
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TxDMA::Idle(Some(TxDMAIdle { tx, buffer }))
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}
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fn start_sending(&mut self, tx_universe: &[u8]) {
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let TxDMA::Idle(idle) = self else {
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return;
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};
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let Some(TxDMAIdle { tx, buffer }) = idle.take() else {
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panic!();
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};
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buffer.copy_from_slice(tx_universe);
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*self = TxDMA::Busy(Some(TxDMABusy {
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transfer: tx.write(buffer),
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}));
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}
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fn wait(&mut self) {
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let TxDMA::Busy(busy) = self else {
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return;
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};
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let Some(TxDMABusy { transfer }) = busy.take() else {
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panic!();
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};
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let (buffer, tx) = transfer.wait();
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*self = TxDMA::Idle(Some(TxDMAIdle { tx, buffer }));
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}
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fn is_idle(&mut self) -> bool {
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match self {
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TxDMA::Idle(_) => true,
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TxDMA::Busy(busy) => {
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let Some(TxDMABusy { transfer }) = busy.take() else {
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panic!();
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};
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let is_done = transfer.is_done();
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busy.replace(TxDMABusy { transfer });
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if is_done {
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self.wait();
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}
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is_done
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}
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}
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}
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}
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#[allow(clippy::upper_case_acronyms)]
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pub struct DMX<const DMX_LEN: usize> {
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tx_universe: DMXUniverse<DMX_LEN>,
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sender: TxDMA<DMX_LEN>,
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}
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impl<const DMX_LEN: usize> DMX<DMX_LEN> {
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pub fn new<PINS>(
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mut serial: serial::Serial<pac::USART1, PINS>,
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channel: dma::dma1::C4,
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pub fn new(
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mem: &'static mut [u8],
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mut dma_channel: dma::dma1::C4,
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pa9: gpio::PA9,
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pa10: gpio::PA10,
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acrh: &mut gpio::Cr<'A', true>,
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mapr: &mut afio::MAPR,
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clocks: &rcc::Clocks,
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) -> Self
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where
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PINS: serial::Pins<pac::USART1>,
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{
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assert!(DMX_LEN <= DMX_LEN_MAX);
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) -> Self {
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// use provided memory region
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assert!(mem.len() >= DMX_LEN * 2);
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serial.reconfigure(250_000.bps(), &clocks).unwrap();
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let (tx_universe, tx_buffer) = {
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let (tx_universe, rest) = mem.split_at_mut(DMX_LEN);
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let (tx_buffer, _) = rest.split_at_mut(DMX_LEN);
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Self::Idle(Some(serial.tx.with_dma(channel)), None)
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}
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let tx_universe: DMXUniverse<DMX_LEN> = tx_universe.try_into().unwrap();
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let tx_buffer: DMXUniverse<DMX_LEN> = tx_buffer.try_into().unwrap();
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pub fn send(&mut self, data: &[u8]) {
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if let Self::Busy(_) = self {
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self.wait();
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}
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let Self::Idle(tx, txbuffer) = self else {
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panic!("Broken DMX State!")
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(tx_universe, tx_buffer)
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};
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let txbuffer = txbuffer.take().unwrap_or_else(|| {
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let foo = singleton!(: [u8; DMX_LEN_MAX] = [0u8; DMX_LEN_MAX]).unwrap();
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(&mut foo[..DMX_LEN]).try_into().unwrap()
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});
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let tx = tx.take().unwrap();
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// setup DMA1_CHANNEL4 interrupt on TransferComplete
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dma_channel.listen(dma::Event::TransferComplete);
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unsafe {
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pac::CorePeripherals::steal()
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.NVIC
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.set_priority(pac::Interrupt::DMA1_CHANNEL4, 1);
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}
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txbuffer.copy_from_slice(&data[..DMX_LEN]);
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*self = Self::Busy(Some(tx.write(txbuffer)));
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// Serial config
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let serial = serial::Serial::new(
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unsafe { pac::Peripherals::steal() }.USART1,
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(
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pa9.into_alternate_open_drain(acrh),
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pa10, //.into_pull_up_input(acrh),
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),
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mapr,
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250_000.bps(),
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clocks,
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);
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Self {
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tx_universe,
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sender: TxDMA::new(serial.tx.with_dma(dma_channel), tx_buffer),
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}
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}
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pub fn wait(&mut self) {
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let Self::Busy(xfer) = self else { return };
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pub fn start_tx(&mut self) {
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self.sender.start_sending(self.tx_universe);
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}
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let xfer = xfer.take().unwrap();
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let (txbuffer, tx) = xfer.wait();
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pub fn wait_tx(&mut self) {
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self.sender.wait();
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}
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*self = Self::Idle(Some(tx), Some(txbuffer));
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pub fn tx_is_idle(&mut self) -> bool {
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self.sender.is_idle()
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}
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}
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@ -1,142 +0,0 @@
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use stm32f1xx_hal::{afio, dma, gpio, pac, prelude::*, rcc, serial};
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type TxDma = dma::TxDma<serial::Tx<pac::USART1>, dma::dma1::C4>;
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type DMXUniverse<const DMX_LEN: usize> = &'static mut [u8; DMX_LEN];
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type DMXTransfer<const DMX_LEN: usize> = dma::Transfer<dma::R, DMXUniverse<DMX_LEN>, TxDma>;
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struct TxDMAIdle<const DMX_LEN: usize> {
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tx: TxDma,
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buffer: DMXUniverse<DMX_LEN>,
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}
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struct TxDMABusy<const DMX_LEN: usize> {
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transfer: DMXTransfer<DMX_LEN>,
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}
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enum TxDMA<const DMX_LEN: usize> {
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Idle(Option<TxDMAIdle<DMX_LEN>>),
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Busy(Option<TxDMABusy<DMX_LEN>>),
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}
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impl<const DMX_LEN: usize> TxDMA<DMX_LEN> {
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fn new(tx: TxDma, buffer: DMXUniverse<DMX_LEN>) -> Self {
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TxDMA::Idle(Some(TxDMAIdle { tx, buffer }))
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}
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fn start_sending(&mut self, tx_universe: &[u8]) {
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let TxDMA::Idle(idle) = self else {
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return;
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};
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let Some(TxDMAIdle { tx, buffer }) = idle.take() else {
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panic!();
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};
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buffer.copy_from_slice(tx_universe);
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*self = TxDMA::Busy(Some(TxDMABusy {
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transfer: tx.write(buffer),
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}));
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}
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fn wait(&mut self) {
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let TxDMA::Busy(busy) = self else {
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return;
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};
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let Some(TxDMABusy { transfer }) = busy.take() else {
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panic!();
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};
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let (buffer, tx) = transfer.wait();
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*self = TxDMA::Idle(Some(TxDMAIdle { tx, buffer }));
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}
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fn is_idle(&mut self) -> bool {
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match self {
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TxDMA::Idle(_) => true,
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TxDMA::Busy(busy) => {
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let Some(TxDMABusy { transfer }) = busy.take() else {
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panic!();
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};
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let is_done = transfer.is_done();
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busy.replace(TxDMABusy { transfer });
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if is_done {
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self.wait();
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}
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is_done
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}
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}
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}
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}
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#[allow(clippy::upper_case_acronyms)]
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pub struct DMX<const DMX_LEN: usize> {
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tx_universe: DMXUniverse<DMX_LEN>,
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sender: TxDMA<DMX_LEN>,
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}
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impl<const DMX_LEN: usize> DMX<DMX_LEN> {
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pub fn new(
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mem: &'static mut [u8],
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mut dma_channel: dma::dma1::C4,
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pa9: gpio::PA9,
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pa10: gpio::PA10,
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acrh: &mut gpio::Cr<'A', true>,
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mapr: &mut afio::MAPR,
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clocks: &rcc::Clocks,
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) -> Self {
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// use provided memory region
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assert!(mem.len() >= DMX_LEN * 2);
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let (tx_universe, tx_buffer) = {
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let (tx_universe, rest) = mem.split_at_mut(DMX_LEN);
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let (tx_buffer, _) = rest.split_at_mut(DMX_LEN);
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let tx_universe: DMXUniverse<DMX_LEN> = tx_universe.try_into().unwrap();
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let tx_buffer: DMXUniverse<DMX_LEN> = tx_buffer.try_into().unwrap();
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(tx_universe, tx_buffer)
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};
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// setup DMA1_CHANNEL4 interrupt on TransferComplete
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dma_channel.listen(dma::Event::TransferComplete);
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unsafe {
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pac::CorePeripherals::steal()
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.NVIC
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.set_priority(pac::Interrupt::DMA1_CHANNEL4, 1);
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}
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// Serial config
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let serial = serial::Serial::new(
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unsafe { pac::Peripherals::steal() }.USART1,
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(
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pa9.into_alternate_open_drain(acrh),
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pa10, //.into_pull_up_input(acrh),
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),
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mapr,
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250_000.bps(),
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clocks,
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);
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Self {
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tx_universe,
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sender: TxDMA::new(serial.tx.with_dma(dma_channel), tx_buffer),
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}
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}
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pub fn start_tx(&mut self) {
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self.sender.start_sending(self.tx_universe);
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}
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pub fn wait_tx(&mut self) {
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self.sender.wait();
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}
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pub fn tx_is_idle(&mut self) -> bool {
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self.sender.is_idle()
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}
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}
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@ -4,15 +4,14 @@
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// mod i2c_reg_slave;
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// mod i2c_slave;
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// mod dmx;
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mod dmx2;
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mod dmx;
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// extern crate panic_halt;
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extern crate panic_semihosting;
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#[rtic::app(device = stm32f1xx_hal::pac, dispatchers = [SPI1, SPI2, SPI3])]
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mod app {
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use crate::dmx2::DMX;
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use crate::dmx::DMX;
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use stm32f1xx_hal::{
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gpio::{self, ExtiPin},
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pac,
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