From d7c906684cf7711a46ff8ed5205dd616d185fdd7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=B6rn-Michael?= <40151420+ldericher@users.noreply.github.com> Date: Sat, 23 Mar 2024 14:55:03 +0000 Subject: [PATCH] exti interrupt working --- bluepill-rs/src/main.rs | 36 +++++++++++++++++++++++++++++------- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/bluepill-rs/src/main.rs b/bluepill-rs/src/main.rs index 0b67776..4aab657 100644 --- a/bluepill-rs/src/main.rs +++ b/bluepill-rs/src/main.rs @@ -1,4 +1,4 @@ -#![deny(unsafe_code)] +// #![deny(unsafe_code)] #![no_std] #![no_main] @@ -36,7 +36,7 @@ mod app { } #[init] - fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) { + fn init(mut cx: init::Context) -> (Shared, Local, init::Monotonics) { // Take ownership over the raw flash and rcc devices and convert them into the corresponding // HAL structs let mut flash = cx.device.FLASH.constrain(); @@ -63,10 +63,23 @@ mod app { let mut afio = cx.device.AFIO.constrain(); let dma1 = cx.device.DMA1.split(); - cx.device.EXTI.imr.write(|w| w.mr1().set_bit()); - let _ = gpiob.pb10.into_pull_up_input(&mut gpiob.crh); + // enable EXTI10 for port B + afio.exticr3 + .exticr3() + .write(|w| unsafe { w.exti10().bits(0b0001) }); + // mask EXTI10 + cx.device.EXTI.imr.write(|w| w.mr10().set_bit()); + // EXTI10 on falling edge + cx.device.EXTI.ftsr.write(|w| w.tr10().set_bit()); + + // set EXTI10 priority + unsafe { + // pac::NVIC::unmask(pac::Interrupt::EXTI15_10); + cx.core.NVIC.set_priority(pac::Interrupt::EXTI15_10, 1); + } + // Serial config let serial = serial::Serial::new( cx.device.USART1, @@ -80,6 +93,7 @@ mod app { ); // rtic::pend(pac::Interrupt::DMA1_CHANNEL4); // ??? + // let nvic = cx.device.NVIC_STIR; foo::spawn().unwrap(); ( @@ -124,9 +138,17 @@ mod app { foo::spawn().unwrap(); } - #[task(binds=EXTI0, local = [int_led], shared = [delay_us])] + #[task(binds=EXTI15_10, local = [int_led], shared = [delay_us])] fn bar(mut cx: bar::Context) { - cx.local.int_led.toggle(); - cx.shared.delay_us.lock(|d| d.delay(1.secs())); + let dp = unsafe { pac::Peripherals::steal() }; + + // EXTI10 must be pending + if dp.EXTI.pr.read().pr10().bit() { + cx.local.int_led.toggle(); + cx.shared.delay_us.lock(|d| d.delay(100.millis())); + + // clear EXTI10 pending status + dp.EXTI.pr.write(|w| w.pr10().set_bit()); + } } }