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i2c modules and defmt from OpenEMC

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This commit is contained in:
Jörn-Michael Miehe 2024-03-03 15:49:38 +00:00
parent 4a7f688de9
commit fb40b4ace8
16 changed files with 1695 additions and 1 deletions
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143
bluepill-rs/Cargo.lock generated
View file

@ -35,7 +35,11 @@ version = "0.1.0"
dependencies = [
"cortex-m",
"cortex-m-rt",
"defmt",
"defmt-ringbuf",
"defmt-rtt",
"embedded-hal 1.0.0",
"heapless",
"nb 1.1.0",
"panic-halt",
"stm32f1xx-hal",
@ -53,6 +57,12 @@ dependencies = [
"vcell",
]
[[package]]
name = "byteorder"
version = "1.5.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b"
[[package]]
name = "cortex-m"
version = "0.7.7"
@ -83,7 +93,7 @@ checksum = "f0f6f3e36f203cfedbc78b357fb28730aa2c6dc1ab060ee5c2405e843988d3c7"
dependencies = [
"proc-macro2",
"quote",
"syn",
"syn 1.0.109",
]
[[package]]
@ -92,6 +102,57 @@ version = "1.1.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "7059fff8937831a9ae6f0fe4d658ffabf58f2ca96aa9dec1c889f936f705f216"
[[package]]
name = "defmt"
version = "0.3.6"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3939552907426de152b3c2c6f51ed53f98f448babd26f28694c95f5906194595"
dependencies = [
"bitflags",
"defmt-macros",
]
[[package]]
name = "defmt-macros"
version = "0.3.7"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "18bdc7a7b92ac413e19e95240e75d3a73a8d8e78aa24a594c22cbb4d44b4bbda"
dependencies = [
"defmt-parser",
"proc-macro-error",
"proc-macro2",
"quote",
"syn 2.0.52",
]
[[package]]
name = "defmt-parser"
version = "0.3.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ff4a5fefe330e8d7f31b16a318f9ce81000d8e35e69b93eae154d16d2278f70f"
dependencies = [
"thiserror",
]
[[package]]
name = "defmt-ringbuf"
version = "0.2.0"
dependencies = [
"cortex-m",
"critical-section",
"defmt",
]
[[package]]
name = "defmt-rtt"
version = "0.4.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "609923761264dd99ed9c7d209718cda4631c5fe84668e0f0960124cbb844c49f"
dependencies = [
"critical-section",
"defmt",
]
[[package]]
name = "embedded-dma"
version = "0.2.0"
@ -142,6 +203,25 @@ version = "2.3.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "1d758ba1b47b00caf47f24925c0074ecb20d6dfcffe7f6d53395c0465674841a"
[[package]]
name = "hash32"
version = "0.3.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "47d60b12902ba28e2730cd37e95b8c9223af2808df9e902d4df49588d1470606"
dependencies = [
"byteorder",
]
[[package]]
name = "heapless"
version = "0.8.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0bfb9eb618601c89945a70e254898da93b13be0388091d42117462b265bb3fad"
dependencies = [
"hash32",
"stable_deref_trait",
]
[[package]]
name = "nb"
version = "0.1.3"
@ -163,6 +243,30 @@ version = "0.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "de96540e0ebde571dc55c73d60ef407c653844e6f9a1e2fdbd40c07b9252d812"
[[package]]
name = "proc-macro-error"
version = "1.0.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a5ce38c"
dependencies = [
"proc-macro-error-attr",
"proc-macro2",
"quote",
"syn 1.0.109",
"version_check",
]
[[package]]
name = "proc-macro-error-attr"
version = "1.0.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b35f869"
dependencies = [
"proc-macro2",
"quote",
"version_check",
]
[[package]]
name = "proc-macro2"
version = "1.0.78"
@ -265,6 +369,37 @@ dependencies = [
"unicode-ident",
]
[[package]]
name = "syn"
version = "2.0.52"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b699d15b36d1f02c3e7c69f8ffef53de37aefae075d8488d4ba1a7788d574a07"
dependencies = [
"proc-macro2",
"quote",
"unicode-ident",
]
[[package]]
name = "thiserror"
version = "1.0.57"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "1e45bcbe8ed29775f228095caf2cd67af7a4ccf756ebff23a306bf3e8b47b24b"
dependencies = [
"thiserror-impl",
]
[[package]]
name = "thiserror-impl"
version = "1.0.57"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a953cb265bef375dae3de6663da4d3804eee9682ea80d8e2542529b73c531c81"
dependencies = [
"proc-macro2",
"quote",
"syn 2.0.52",
]
[[package]]
name = "unicode-ident"
version = "1.0.12"
@ -283,6 +418,12 @@ version = "0.1.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
[[package]]
name = "version_check"
version = "0.9.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f"
[[package]]
name = "void"
version = "1.0.2"

5
bluepill-rs/Cargo.toml
View file

@ -6,10 +6,15 @@ edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
defmt-ringbuf = { path = "../defmt-ringbuf", optional = true }
embedded-hal = "1.0.0"
nb = "1"
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = { version = "0.7.1", features = ["device"] }
defmt = { version = "0.3", features = ["encoding-rzcobs"] }
defmt-rtt = { version = "0.4", optional = true }
heapless = "0.8.0"
# Panic behaviour, see https://crates.io/keywords/panic-impl for alternatives
panic-halt = "0.2.0"

360
bluepill-rs/src/i2c_reg_slave.rs Normal file
View file

@ -0,0 +1,360 @@
//! I2C register slave.
use core::ops::Deref;
use heapless::Vec;
use crate::i2c_slave::{self, Event as I2cEvent, I2cSlave, Instance};
/// I2C register slave error.
#[derive(Eq, PartialEq)]
#[non_exhaustive]
pub enum Error {
/// The buffer overflowed during reception.
BufferOverrun,
/// An I2C error occurred.
I2c(i2c_slave::Error),
}
impl From<i2c_slave::Error> for Error {
fn from(err: i2c_slave::Error) -> Self {
Self::I2c(err)
}
}
/// I2C slave using the register access model.
pub struct I2CRegSlave<I2C, PINS, const BUFFER: usize> {
slave: I2cSlave<I2C, PINS>,
reg: u8,
state: State,
buf: [u8; BUFFER],
pos: usize,
}
/// State of register slave.
#[derive(Clone, Copy)]
enum State {
/// Idle.
Idle,
/// Expecting to receive register.
ReceiveReg,
/// Register value received, waiting for write or read restart.
ReceivedReg,
/// Receiving register value.
Receiving,
/// Received read request, waiting for register value.
StartSend,
/// Sending register value.
Sending,
/// Waiting for end.
Clear,
}
impl<I2C, PINS, const BUFFER: usize> I2CRegSlave<I2C, PINS, BUFFER>
where
I2C: Instance,
{
/// Initializes the I2C register slave.
pub fn new(slave: I2cSlave<I2C, PINS>) -> Self {
Self {
slave,
reg: 0,
state: State::Idle,
buf: [0; BUFFER],
pos: 0,
}
}
/// Releases the I2C slave.
pub fn into_inner(self) -> I2cSlave<I2C, PINS> {
self.slave
}
/// Accesses the I2C slave.
///
/// This should not be used to process events, as doing so would
/// confuse the state of the I2C register model.
pub fn as_mut(&mut self) -> &mut I2cSlave<I2C, PINS> {
&mut self.slave
}
fn i2c_event(&mut self) -> nb::Result<i2c_slave::Event<I2C, PINS>, Error> {
match self.slave.event() {
Ok(evt) => Ok(evt),
Err(nb::Error::WouldBlock) => Err(nb::Error::WouldBlock),
Err(nb::Error::Other(err)) => {
self.state = State::Idle;
Err(nb::Error::Other(err.into()))
}
}
}
/// Gets the next event.
pub fn event(&mut self) -> nb::Result<Event<BUFFER>, Error> {
loop {
match &mut self.state {
State::Idle => match self.i2c_event()? {
I2cEvent::StartRead => self.state = State::ReceiveReg,
I2cEvent::StartWrite => {
self.state = State::StartSend;
self.pos = 0;
return Ok(Event::Read { reg: self.reg });
}
_ => defmt::unreachable!(),
},
State::ReceiveReg => match self.i2c_event()? {
I2cEvent::Read(value) => {
self.reg = value;
self.state = State::ReceivedReg;
}
I2cEvent::End | I2cEvent::Restart => self.state = State::Idle,
_ => defmt::unreachable!(),
},
State::ReceivedReg => match self.i2c_event()? {
I2cEvent::Read(value) => {
if !self.buf.is_empty() {
self.buf[0] = value;
self.pos = 1;
self.state = State::Receiving;
} else {
self.state = State::Clear;
return Err(nb::Error::Other(Error::BufferOverrun));
}
}
I2cEvent::End => {
self.state = State::Idle;
return Ok(Event::Write {
reg: self.reg,
value: Value(Vec::new()),
});
}
I2cEvent::Restart => self.state = State::Idle,
_ => defmt::unreachable!(),
},
State::Receiving => match self.i2c_event()? {
I2cEvent::Read(value) => {
if self.pos < self.buf.len() {
self.buf[self.pos] = value;
self.pos += 1;
} else {
return Err(nb::Error::Other(Error::BufferOverrun));
}
}
I2cEvent::End | I2cEvent::Restart => {
self.state = State::Idle;
return Ok(Event::Write {
reg: self.reg,
value: Value(defmt::unwrap!(Vec::try_from(&self.buf[..self.pos]))),
});
}
_ => defmt::unreachable!(),
},
State::StartSend => return Ok(Event::Read { reg: self.reg }),
State::Sending => {
let to_send = self.buf.get(self.pos).cloned().unwrap_or_default();
match self.i2c_event()? {
I2cEvent::Write(w) => {
w.write(to_send);
self.pos += 1;
}
I2cEvent::End | I2cEvent::Restart => self.state = State::Idle,
_ => defmt::unreachable!(),
}
}
State::Clear => match self.i2c_event()? {
I2cEvent::End => self.state = State::Idle,
I2cEvent::Write(w) => w.write(0),
_ => (),
},
}
}
}
/// Responds to a read register event.
pub fn respond(&mut self, response: Response<BUFFER>) {
if let State::StartSend = &self.state {
let n = response.0.len();
self.buf[..n].copy_from_slice(&response.0);
self.buf[n..].fill(0);
self.pos = 0;
self.state = State::Sending;
} else {
defmt::panic!("I2C register slave had no read register event")
}
}
}
/// I2C register slave event.
pub enum Event<const BUFFER: usize> {
/// Write register.
Write {
/// Register.
reg: u8,
/// Register value written by I2C master.
value: Value<BUFFER>,
},
/// Read register.
///
/// Call [`I2CRegSlave`] with your reply.
Read {
/// Register.
reg: u8,
},
}
/// The value written into an I2C register.
#[derive(Clone)]
pub struct Value<const BUFFER: usize>(pub Vec<u8, BUFFER>);
impl<const BUFFER: usize> Deref for Value<BUFFER> {
type Target = [u8];
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl<const BUFFER: usize> Value<BUFFER> {
fn get_or_zero(&self, idx: usize) -> u8 {
self.get(idx).cloned().unwrap_or_default()
}
/// Gets the register value as an u8.
///
/// Missing bytes are treated as zero and superflous bytes are ignored.
pub fn as_u8(&self) -> u8 {
self.get_or_zero(0)
}
/// Gets the register value as an u16 with LSB first.
///
/// Missing bytes are treated as zero and superflous bytes are ignored.
pub fn as_u16(&self) -> u16 {
let b = self.get_or_zero(0) as u16;
let a = self.get_or_zero(1) as u16;
(a << 8) | b
}
/// Gets the register value as an u32 with LSB first.
///
/// Missing bytes are treated as zero and superflous bytes are ignored.
pub fn as_u32(&self) -> u32 {
let d = self.get_or_zero(0) as u32;
let c = self.get_or_zero(1) as u32;
let b = self.get_or_zero(2) as u32;
let a = self.get_or_zero(3) as u32;
(a << 24) | (b << 16) | (c << 8) | d
}
/// Gets the register value as an u64 with LSB first.
///
/// Missing bytes are treated as zero and superflous bytes are ignored.
pub fn as_u64(&self) -> u64 {
let h = self.get_or_zero(0) as u64;
let g = self.get_or_zero(1) as u64;
let f = self.get_or_zero(2) as u64;
let e = self.get_or_zero(3) as u64;
let d = self.get_or_zero(4) as u64;
let c = self.get_or_zero(5) as u64;
let b = self.get_or_zero(6) as u64;
let a = self.get_or_zero(7) as u64;
(a << 56) | (b << 48) | (c << 40) | (d << 32) | (e << 24) | (f << 16) | (g << 8) | h
}
}
/// Response to register read request.
pub struct Response<const BUFFER: usize>(pub Vec<u8, BUFFER>);
impl<const BUFFER: usize> From<Vec<u8, BUFFER>> for Response<BUFFER> {
fn from(value: Vec<u8, BUFFER>) -> Self {
Self(value)
}
}
impl<const BUFFER: usize> Deref for Response<BUFFER> {
type Target = [u8];
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl<const BUFFER: usize> Response<BUFFER> {
/// Provides the register value.
///
/// The length of the value must not exceed `BUFFER`.
pub fn set(value: &[u8]) -> Self {
defmt::assert!(value.len() <= BUFFER);
Self(defmt::unwrap!(value.try_into()))
}
/// Provides an empty register value which will read as all zeros.
pub fn set_empty() -> Self {
Self::set(&[])
}
/// Provides the register value, clipping the provided value as necessary.
pub fn set_clipped(value: &[u8]) -> Self {
if value.len() <= BUFFER {
Self::set(value)
} else {
Self::set(&value[..BUFFER])
}
}
/// Sets the register value to an u8.
pub fn set_u8(value: u8) -> Self {
Self::set(&[value])
}
/// Sets the register value to an u16 with LSB first.
pub fn set_u16(value: u16) -> Self {
Self::set(&[(value & 0xff) as u8, ((value >> 8) & 0xff) as u8])
}
/// Sets the register value to an u32 with LSB first.
pub fn set_u32(value: u32) -> Self {
Self::set(&[
(value & 0xff) as u8,
((value >> 8) & 0xff) as u8,
((value >> 16) & 0xff) as u8,
((value >> 24) & 0xff) as u8,
])
}
/// Sets the register value to an u64 with LSB first.
pub fn set_u64(value: u64) -> Self {
Self::set(&[
(value & 0xff) as u8,
((value >> 8) & 0xff) as u8,
((value >> 16) & 0xff) as u8,
((value >> 24) & 0xff) as u8,
((value >> 32) & 0xff) as u8,
((value >> 40) & 0xff) as u8,
((value >> 48) & 0xff) as u8,
((value >> 56) & 0xff) as u8,
])
}
/// Sets the register value to an u128 with LSB first.
pub fn set_u128(value: u128) -> Self {
Self::set(&[
(value & 0xff) as u8,
((value >> 8) & 0xff) as u8,
((value >> 16) & 0xff) as u8,
((value >> 24) & 0xff) as u8,
((value >> 32) & 0xff) as u8,
((value >> 40) & 0xff) as u8,
((value >> 48) & 0xff) as u8,
((value >> 56) & 0xff) as u8,
((value >> 64) & 0xff) as u8,
((value >> 72) & 0xff) as u8,
((value >> 80) & 0xff) as u8,
((value >> 88) & 0xff) as u8,
((value >> 96) & 0xff) as u8,
((value >> 104) & 0xff) as u8,
((value >> 112) & 0xff) as u8,
((value >> 120) & 0xff) as u8,
])
}
}

298
bluepill-rs/src/i2c_slave.rs Normal file
View file

@ -0,0 +1,298 @@
//! I2C slave driver with interrupt support.
#![allow(unsafe_code)]
use core::ops::Deref;
use stm32f1xx_hal::{
afio::MAPR,
gpio::{self, Alternate, OpenDrain},
pac::{I2C1, I2C2, RCC},
rcc::{BusClock, Clocks, Enable, Reset},
time::Hertz,
};
/// I2C slave error.
#[derive(Eq, PartialEq)]
#[non_exhaustive]
pub enum Error {
/// Bus error
Bus,
}
/// Helper trait to ensure that the correct I2C pins are used for the corresponding interface
pub trait Pins<I2C> {
const REMAP: bool;
}
impl Pins<I2C1>
for (
gpio::PB6<Alternate<OpenDrain>>,
gpio::PB7<Alternate<OpenDrain>>,
)
{
const REMAP: bool = false;
}
impl Pins<I2C1>
for (
gpio::PB8<Alternate<OpenDrain>>,
gpio::PB9<Alternate<OpenDrain>>,
)
{
const REMAP: bool = true;
}
impl Pins<I2C2>
for (
gpio::PB10<Alternate<OpenDrain>>,
gpio::PB11<Alternate<OpenDrain>>,
)
{
const REMAP: bool = false;
}
/// I2C peripheral operating in slave mode.
///
/// Only a single 7-bit address is supported.
pub struct I2cSlave<I2C, PINS> {
i2c: I2C,
pins: PINS,
addr: u8,
pclk1: Hertz,
state: State,
}
#[derive(Clone, Copy)]
enum State {
Idle,
Receiving,
Sending,
WriteWaiting,
}
pub trait Instance:
Deref<Target = stm32f1xx_hal::pac::i2c1::RegisterBlock> + Enable + Reset + BusClock
{
}
impl Instance for I2C1 {}
impl Instance for I2C2 {}
impl<PINS> I2cSlave<I2C1, PINS> {
/// Creates a generic I2C1 object on pins PB6 and PB7 or PB8 and PB9 (if remapped)
pub fn i2c1(i2c: I2C1, pins: PINS, mapr: &mut MAPR, addr: u8, clocks: Clocks) -> Self
where
PINS: Pins<I2C1>,
{
mapr.modify_mapr(|_, w| w.i2c1_remap().bit(PINS::REMAP));
I2cSlave::<I2C1, _>::configure(i2c, pins, addr, clocks)
}
}
impl<PINS> I2cSlave<I2C2, PINS> {
/// Creates a generic I2C2 object on pins PB10 and PB11.
pub fn i2c2(i2c: I2C2, pins: PINS, addr: u8, clocks: Clocks) -> Self
where
PINS: Pins<I2C2>,
{
I2cSlave::<I2C2, _>::configure(i2c, pins, addr, clocks)
}
}
impl<I2C, PINS> I2cSlave<I2C, PINS>
where
I2C: Instance,
{
/// Configures the I2C peripheral to work in slave mode.
fn configure(i2c: I2C, pins: PINS, addr: u8, clocks: Clocks) -> Self {
let rcc = unsafe { &(*RCC::ptr()) };
I2C::enable(rcc);
I2C::reset(rcc);
let mut i2c = Self {
i2c,
pins,
addr,
pclk1: I2C::clock(&clocks),
state: State::Idle,
};
i2c.reset();
i2c
}
}
impl<I2C, PINS> I2cSlave<I2C, PINS>
where
I2C: Instance,
{
/// Initializes I2C.
///
/// Configures the `I2C_CRX` registers according to the system frequency.
fn init(&mut self) {
self.i2c.cr1.write(|w| w.pe().clear_bit());
let pclk1_mhz = self.pclk1.to_MHz() as u16;
self.i2c
.cr2
.write(|w| unsafe { w.freq().bits(pclk1_mhz as u8) });
self.i2c
.oar1
.write(|w| w.add().bits((self.addr as u16) << 1));
self.i2c.cr1.modify(|_, w| w.pe().enabled().ack().ack());
}
/// Perform an I2C software reset
fn reset(&mut self) {
self.i2c.cr1.write(|w| w.pe().set_bit().swrst().set_bit());
self.i2c.cr1.reset();
self.init();
}
/// Delay execution by reading SR1.
///
/// Workaround for I2C controller bugs.
fn sr1_delay(&mut self) {
for _ in 0..100 {
self.i2c.sr1.read();
}
}
/// Gets the next event.
pub fn event(&mut self) -> nb::Result<Event<I2C, PINS>, Error> {
let sr1 = self.i2c.sr1.read();
if sr1.berr().is_error() {
self.i2c.sr1.modify(|_, w| w.berr().clear_bit());
return Err(Error::Bus.into());
}
match self.state {
State::Idle => {
if sr1.addr().is_match() {
self.i2c.sr1.read();
let sr2 = self.i2c.sr2.read();
if sr2.tra().bit_is_set() {
self.state = State::Sending;
Ok(Event::StartWrite)
} else {
self.state = State::Receiving;
self.i2c.cr1.modify(|_, w| w.ack().ack());
Ok(Event::StartRead)
}
} else {
Err(nb::Error::WouldBlock)
}
}
State::Sending => {
if sr1.af().is_failure() {
self.i2c.sr1.modify(|_, w| w.af().no_failure());
self.state = State::Idle;
Ok(Event::End)
} else if sr1.tx_e().is_empty() {
self.state = State::WriteWaiting;
Ok(Event::Write(Writer(self)))
} else {
Err(nb::Error::WouldBlock)
}
}
State::WriteWaiting => defmt::panic!("write event was not handled"),
State::Receiving => {
if sr1.rx_ne().is_not_empty() {
let value = self.i2c.dr.read().dr().bits();
Ok(Event::Read(value))
} else if sr1.stopf().is_stop() || sr1.tx_e().is_empty() {
self.i2c.sr1.read();
self.i2c.cr1.modify(|_, w| w.pe().enabled().ack().ack());
self.state = State::Idle;
if sr1.tx_e().is_empty() {
// Workaround for I2C bus hanging after restart condition.
self.sr1_delay();
Ok(Event::Restart)
} else {
Ok(Event::End)
}
} else {
Err(nb::Error::WouldBlock)
}
}
}
}
/// Enables triggering the event interrupt (I2Cx_EV) when the transmit buffer is
/// empty or the receive buffer is not empty.
///
/// The event interrupt must be enabled separately using [`listen_event`](Self::listen_event).
pub fn listen_buffer(&mut self) {
self.i2c.cr2.modify(|_, w| w.itbufen().enabled());
}
/// Disables triggering the event interrupt (I2Cx_EV) when the transmit buffer is
/// empty or the receive buffer is not empty.
pub fn unlisten_buffer(&mut self) {
self.i2c.cr2.modify(|_, w| w.itbufen().disabled());
}
/// Enables triggering the event interrupt (I2Cx_EV) when the address is matched,
/// stop is detected, the byte transfer is finished or an event
/// described in [`listen_buffer`](Self::listen_buffer) occurrs.
pub fn listen_event(&mut self) {
self.i2c.cr2.modify(|_, w| w.itevten().enabled());
}
/// Disables triggering the event interrupt (I2Cx_EV) when the address is matched,
/// stop is detected, the byte transfer is finished or an event
/// described in [unlisten_buffer](Self::unlisten_buffer) occurrs.
pub fn unlisten_event(&mut self) {
self.i2c.cr2.modify(|_, w| w.itevten().disabled());
}
/// Enables triggering the error interrupt (I2Cx_ER) when an error is detected.
pub fn listen_error(&mut self) {
self.i2c.cr2.modify(|_, w| w.iterren().enabled());
}
/// Disables triggering the error interrupt (I2Cx_ER) when an error is detected.
pub fn unlisten_error(&mut self) {
self.i2c.cr2.modify(|_, w| w.iterren().disabled());
}
/// Releases the I2C peripheral and associated pins.
pub fn release(self) -> (I2C, PINS) {
(self.i2c, self.pins)
}
}
/// An I2C slave event.
pub enum Event<'a, I2C, PINS> {
/// Start of reception from the I2C master.
StartRead,
/// Start of transmission to the I2C master.
StartWrite,
/// A byte has been received from the I2C master.
Read(u8),
/// A byte must be transmitted to the I2C master.
Write(Writer<'a, I2C, PINS>),
/// End of reception and start of transmission.
Restart,
/// End of transfer.
End,
}
/// Transmits a byte to the I2C master.
pub struct Writer<'a, I2C, PINS>(&'a mut I2cSlave<I2C, PINS>);
impl<'a, I2C, PINS> Writer<'a, I2C, PINS>
where
I2C: Instance,
{
/// Sends the specified value to the I2C master.
pub fn write(self, value: u8) {
self.0.i2c.dr.write(|w| w.dr().bits(value));
self.0.state = State::Sending;
}
}

3
bluepill-rs/src/main.rs
View file

@ -17,6 +17,9 @@ use nb::block;
use cortex_m_rt::entry;
use stm32f1xx_hal::{pac, prelude::*, rcc, serial, timer::Timer};
mod i2c_reg_slave;
mod i2c_slave;
#[entry]
fn main() -> ! {
// Get access to the core peripherals from the cortex-m crate

248
defmt-ringbuf/Cargo.lock generated Normal file
View file

@ -0,0 +1,248 @@
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20
defmt-ringbuf/Cargo.toml Normal file
View file

@ -0,0 +1,20 @@
[package]
name = "defmt-ringbuf"
description = "defmt persistent ring buffer logger"
authors = ["Sebastian Urban <surban@surban.net>"]
categories = ["embedded", "no-std"]
keywords = ["defmt", "defmt-transport"]
readme = "README.md"
repository = "https://github.com/surban/openemc"
license = "MIT OR Apache-2.0"
version = "0.2.0"
edition = "2021"
[features]
default = ["logger"]
logger = []
[dependencies]
defmt = "0.3"
critical-section = "1"
cortex-m = "0.7"

201
defmt-ringbuf/LICENSE-APACHE Normal file
View file

@ -0,0 +1,201 @@
Apache License
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TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
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23
defmt-ringbuf/LICENSE-MIT Normal file
View file

@ -0,0 +1,23 @@
Permission is hereby granted, free of charge, to any
person obtaining a copy of this software and associated
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limitation the rights to use, copy, modify, merge,
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.

21
defmt-ringbuf/README.md Normal file
View file

@ -0,0 +1,21 @@
# defmt-ringbuf
This crate stores [`defmt`] log messages in a simple ring buffer that is persisted across resets.
You still need to read the messages from the buffer and transfer them to a host for formatting.
[`defmt`]: https://github.com/knurling-rs/defmt
## License
Licensed under either of
- [Apache License, Version 2.0](LICENSE-APACHE)
- [MIT license](LICENSE-MIT)
at your option.
## Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in defmt-ringbuf by you shall be licensed as above,
without any additional terms or conditions.

10
defmt-ringbuf/defmt-ringbuf-test/.cargo/config.toml Normal file
View file

@ -0,0 +1,10 @@
[build]
target = "thumbv7m-none-eabi"
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "link-arg=--nmagic",
"-C", "link-arg=-Tdefmt.x",
]
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
runner = "probe-run --chip STM32F103RB"

22
defmt-ringbuf/defmt-ringbuf-test/Cargo.toml Normal file
View file

@ -0,0 +1,22 @@
[package]
name = "defmt-ringbuf-test"
authors = ["Sebastian Urban <surban@surban.net>"]
license = "GPL-3.0"
version = "0.0.0"
publish = false
edition = "2021"
[dependencies]
defmt-ringbuf = { path = "..", default-features = false }
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
cortex-m-rt = { version = "0.7", features = ["device"] }
stm32f1 = { version = "0.15", features = ["stm32f103", "rt"] }
panic-probe = "0.3"
defmt = "0.3"
defmt-rtt = "0.4"
[profile.release]
opt-level = 'z'
lto = true
debug = 2

5
defmt-ringbuf/defmt-ringbuf-test/memory.x Normal file
View file

@ -0,0 +1,5 @@
MEMORY
{
FLASH : ORIGIN = 0x08000000, LENGTH = 64K
RAM : ORIGIN = 0x20000000, LENGTH = 20K
}

42
defmt-ringbuf/defmt-ringbuf-test/src/main.rs Normal file
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#![no_std]
#![no_main]
use core::mem;
use cortex_m::{asm::nop, peripheral::SCB};
use cortex_m_rt::entry;
use defmt_ringbuf::{RingBuf, RingBuffer};
use defmt_rtt as _;
use panic_probe as _;
use stm32f1::stm32f103::Peripherals;
#[no_mangle]
#[used]
#[link_section = ".uninit.BUFFER"]
pub static mut BUFFER: mem::MaybeUninit<defmt_ringbuf::RingBuffer<4096>> = mem::MaybeUninit::uninit();
#[entry]
fn main() -> ! {
let _dp = Peripherals::take().unwrap();
defmt::info!("Init");
let buffer = unsafe { RingBuffer::init(&mut BUFFER) };
let mut data = [0; 128];
let (n, lost) = buffer.read(&mut data);
let data = &data[..n];
defmt::info!("Buffer contents (lost={}): {}", lost, data);
let mut data = [0; 255];
for (i, d) in data.iter_mut().enumerate() {
*d = i as u8;
}
buffer.write(&data);
defmt::info!("Wrote {} bytes to buffer", data.len());
defmt::info!("Done");
for _ in 0..1_000_000 {
nop();
}
SCB::sys_reset();
}

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defmt-ringbuf/src/lib.rs Normal file
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//! defmt-ringbuf is a [`defmt`](https://github.com/knurling-rs/defmt) global logger that logs into
//! a persistent ring buffer.
//!
//! The ring buffer is not cleared at startup, i.e. if placed in a static global variable log messages
//! will still be available after a reset.
//!
//! To use this crate, link to it by importing it somewhere in your project.
//!
//! ```
//! use core::mem::MaybeUninit;
//! use defmt_ringbuf as _;
//!
//! static mut LOG: MaybeUninit<defmt_ringbuf::RingBuffer<1024>> = MaybeUninit::uninit();
//!
//! #[entry]
//! fn main() -> ! {
//! unsafe {
//! defmt_ringbuf::init(&mut LOG, || ());
//! }
//!
//! // ...
//! }
//! ```
//!
//! Call [init] to initialize logging and [read] to read buffered log data.
//!
//! # Critical section implementation
//!
//! This crate uses [`critical-section`](https://github.com/rust-embedded/critical-section) to ensure only one thread
//! is writing to the buffer at a time. You must import a crate that provides a `critical-section` implementation
//! suitable for the current target. See the `critical-section` README for details.
//!
//! For example, for single-core privileged-mode Cortex-M targets, you can add the following to your Cargo.toml.
//!
//! ```toml
//! [dependencies]
//! cortex-m = { version = "0.7.6", features = ["critical-section-single-core"]}
//! ```
#![no_std]
use core::{
mem::MaybeUninit,
sync::atomic::{AtomicBool, Ordering},
};
mod ring_buffer;
pub use ring_buffer::{RingBuf, RingBuffer};
#[cfg_attr(feature = "logger", defmt::global_logger)]
struct Logger;
/// Global logger lock.
static TAKEN: AtomicBool = AtomicBool::new(false);
/// Crticial section.
static mut CS_RESTORE: critical_section::RestoreState = critical_section::RestoreState::invalid();
/// Encoder.
static mut ENCODER: defmt::Encoder = defmt::Encoder::new();
/// Ring buffer.
static mut RING_BUFFER: Option<&'static mut dyn RingBuf> = None;
/// Callback when new log data is available.
static mut LOG_AVAILABLE: fn() = || ();
unsafe impl defmt::Logger for Logger {
fn acquire() {
let restore = unsafe { critical_section::acquire() };
if TAKEN.load(Ordering::Relaxed) {
panic!("defmt logger taken reentrantly")
}
TAKEN.store(true, Ordering::Relaxed);
unsafe { CS_RESTORE = restore };
unsafe { ENCODER.start_frame(do_write) }
}
unsafe fn flush() {
// Flush is a no-op.
}
unsafe fn release() {
ENCODER.end_frame(do_write);
TAKEN.store(false, Ordering::Relaxed);
let restore = CS_RESTORE;
critical_section::release(restore);
}
unsafe fn write(bytes: &[u8]) {
ENCODER.write(bytes, do_write);
}
}
fn do_write(data: &[u8]) {
unsafe {
if let Some(buffer) = RING_BUFFER.as_mut() {
buffer.write(data);
LOG_AVAILABLE();
}
}
}
/// Initializes logging to a ring buffer.
///
/// `ring_buffer` specifies the location of the log buffer.
/// It is not cleared if it contains vailid data from the previous boot.
///
/// `log_available` is called when new log messages are available.
///
/// This must be called exactly once.
/// Log messages received before initiailization are discarded.
pub unsafe fn init<const SIZE: usize>(
ring_buffer: &'static mut MaybeUninit<RingBuffer<SIZE>>,
log_available: fn(),
) {
defmt::assert!(RING_BUFFER.is_none());
let ring_buffer = RingBuffer::init(ring_buffer);
RING_BUFFER = Some(ring_buffer as &mut dyn RingBuf);
LOG_AVAILABLE = log_available;
}
/// Reads and removes data from the log buffer.
///
/// Returns the number of bytes read and whether data was lost.
pub fn read(data: &mut [u8]) -> (usize, bool) {
unsafe {
critical_section::with(|_cs| {
if let Some(buffer) = RING_BUFFER.as_mut() {
buffer.read(data)
} else {
(0, false)
}
})
}
}

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defmt-ringbuf/src/ring_buffer.rs Normal file
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//! Ring buffer.
use core::{
mem::MaybeUninit,
ptr::{addr_of, addr_of_mut},
sync::atomic::{AtomicBool, AtomicU32, AtomicU8, AtomicUsize, Ordering},
};
use cortex_m::Peripherals;
/// Ring buffer access methods.
pub trait RingBuf {
/// Write into the ring buffer.
fn write(&mut self, data: &[u8]);
/// Read from the ring buffer.
///
/// Returns the number of bytes read and whether data was lost.
fn read(&mut self, data: &mut [u8]) -> (usize, bool);
}
/// Ring buffer.
#[repr(C)]
pub struct RingBuffer<const SIZE: usize> {
/// Signature for validity check.
signature: AtomicU32,
/// Read position.
read_pos: AtomicUsize,
/// Write position.
write_pos: AtomicUsize,
/// Unread data overwritten?
overwritten: AtomicBool,
/// Buffer.
buf: [AtomicU8; SIZE],
}
impl<const SIZE: usize> RingBuffer<SIZE> {
/// Signature for validity check.
const SIGNATURE: u32 = 0xb0ffe300;
/// Initializes the ring buffer, keeping its data if it appears valid.
pub fn init(uninit: &mut MaybeUninit<Self>) -> &mut Self {
unsafe {
let mut scb = Peripherals::steal().SCB;
let ptr = uninit.as_mut_ptr();
let signature = (addr_of!((*ptr).signature) as *const u32).read_volatile();
let mut read_pos = (addr_of!((*ptr).read_pos) as *const usize).read_volatile();
let mut write_pos = (addr_of!((*ptr).write_pos) as *const usize).read_volatile();
let mut overwritten = (addr_of!((*ptr).overwritten) as *const u8).read_volatile();
let valid = signature == Self::SIGNATURE
&& read_pos < SIZE
&& write_pos < SIZE
&& (overwritten == 0 || overwritten == 1);
if !valid {
addr_of_mut!((*ptr).signature).write_volatile(AtomicU32::new(0));
scb.clean_dcache_by_ref(&(*ptr).signature);
read_pos = 0;
write_pos = 0;
overwritten = 0;
}
for i in 0..SIZE {
let b = if valid { (addr_of!((*ptr).buf[i]) as *const u8).read_volatile() } else { 0 };
addr_of_mut!((*ptr).buf[i]).write_volatile(AtomicU8::new(b));
}
scb.clean_dcache_by_slice(&(*ptr).buf);
addr_of_mut!((*ptr).read_pos).write_volatile(AtomicUsize::new(read_pos));
scb.clean_dcache_by_ref(&(*ptr).read_pos);
addr_of_mut!((*ptr).write_pos).write_volatile(AtomicUsize::new(write_pos));
scb.clean_dcache_by_ref(&(*ptr).write_pos);
addr_of_mut!((*ptr).overwritten).write_volatile(AtomicBool::new(overwritten != 0));
scb.clean_dcache_by_ref(&(*ptr).overwritten);
addr_of_mut!((*ptr).signature).write_volatile(AtomicU32::new(Self::SIGNATURE));
scb.clean_dcache_by_ref(&(*ptr).signature);
// SAFETY: all fields have been initialized with either default values or their previous contents.
uninit.assume_init_mut()
}
}
}
impl<const SIZE: usize> RingBuf for RingBuffer<SIZE> {
fn write(&mut self, mut data: &[u8]) {
let mut scb = unsafe { Peripherals::steal().SCB };
while !data.is_empty() {
// Split data into part that fits remaining buffer.
let write_pos = self.write_pos.load(Ordering::SeqCst);
let to_end = SIZE - write_pos;
let (part, rest) = data.split_at(to_end.min(data.len()));
data = rest;
// Calculate write boundaries.
let from = write_pos;
let to = write_pos + part.len();
// Update read position if we overwrite unread data.
let read_pos = self.read_pos.load(Ordering::SeqCst);
if from < read_pos && to >= read_pos {
self.overwritten.store(true, Ordering::SeqCst);
let mut new_read_pos = to + 1;
if new_read_pos >= SIZE {
new_read_pos = 0;
}
self.read_pos.store(new_read_pos, Ordering::SeqCst);
scb.clean_dcache_by_ref(&self.read_pos);
}
// Copy.
for (dst, src) in self.buf[from..to].iter_mut().zip(part.iter()) {
dst.store(*src, Ordering::SeqCst);
}
scb.clean_dcache_by_slice(&self.buf[from..to]);
// Update write position.
let new_write_pos = if to == SIZE { 0 } else { to };
self.write_pos.store(new_write_pos, Ordering::SeqCst);
scb.clean_dcache_by_ref(&self.write_pos);
}
}
fn read(&mut self, data: &mut [u8]) -> (usize, bool) {
let mut scb = unsafe { Peripherals::steal().SCB };
let read_pos = self.read_pos.load(Ordering::SeqCst);
let write_pos = self.write_pos.load(Ordering::SeqCst);
let overwritten = self.overwritten.load(Ordering::SeqCst);
// Calculate available data.
let avail = if read_pos > write_pos { SIZE - read_pos } else { write_pos - read_pos };
let n = avail.min(data.len());
// Copy.
let from = read_pos;
let to = read_pos + n;
for (dst, src) in data[..n].iter_mut().zip(self.buf[from..to].iter()) {
*dst = src.load(Ordering::SeqCst);
}
// Update read position and overwritten status.
let new_read_pos = if to == SIZE { 0 } else { to };
self.read_pos.store(new_read_pos, Ordering::SeqCst);
scb.clean_dcache_by_ref(&self.read_pos);
self.overwritten.store(false, Ordering::SeqCst);
scb.clean_dcache_by_ref(&self.overwritten);
(n, overwritten)
}
}