streamlining

This commit is contained in:
Jörn-Michael Miehe 2024-03-21 21:04:51 +00:00
parent df790fcc74
commit 91139c792c

View file

@ -9,7 +9,7 @@ mod dmx;
// extern crate panic_halt;
extern crate panic_semihosting;
#[rtic::app(device = stm32f1xx_hal::pac, dispatchers = [DMA1_CHANNEL4])]
#[rtic::app(device = stm32f1xx_hal::pac, dispatchers = [PVD])]
mod app {
use cortex_m::singleton;
use stm32f1xx_hal::{gpio, pac, prelude::*, serial, timer};
@ -24,12 +24,12 @@ mod app {
#[shared]
struct Shared {
buffer: &'static mut [u8; 512],
delay_us: timer::DelayUs<pac::TIM2>,
}
#[local]
struct Local {
dmx: DMX,
delay_us: timer::DelayUs<pac::TIM2>,
led: gpio::gpioc::PC13<gpio::Output>,
}
@ -72,17 +72,18 @@ mod app {
&clocks,
);
// rtic::pend(pac::Interrupt::DMA1_CHANNEL4); // ???
foo::spawn().unwrap();
(
Shared {
buffer: singleton!(: [u8; 512] = [0b01010101; 512]).unwrap(),
},
Local {
dmx: DMX::new(serial, dma1.4, &clocks),
// Configure timer
delay_us: cx.device.TIM2.delay_us(&clocks),
},
Local {
dmx: DMX::new(serial, dma1.4, &clocks),
// Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the function
// in order to configure the port. For pins 0-7, crl should be passed instead.
@ -95,19 +96,16 @@ mod app {
#[idle]
fn idle(_: idle::Context) -> ! {
loop {
cortex_m::asm::nop();
rtic::export::wfi();
}
}
#[task(local = [dmx, delay_us, led], shared = [&buffer])]
fn foo(cx: foo::Context) {
#[task(local = [dmx, led], shared = [&buffer, delay_us])]
fn foo(mut cx: foo::Context) {
cx.local.dmx.send(cx.shared.buffer);
cx.local.led.set_low();
cx.local.delay_us.delay(1.secs());
cx.local.led.set_high();
cx.local.delay_us.delay(1.secs());
cx.local.led.toggle();
cx.shared.delay_us.lock(|d| d.delay(1.secs()));
cx.local.dmx.wait();
foo::spawn().unwrap();